Mario1159/RVSCC
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RISC-V Simple Core Collection
21 Commits 3 Branches 0 Tags 356 KiB
SystemVerilog 79.3%
CMake 14.4%
Assembly 2.6%
C++ 2.1%
Dockerfile 0.8%
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Mario Romero d37e4fb248 Update C toolchain
2022-11-28 04:54:18 -03:00
fw Update C toolchain 2022-11-28 04:54:18 -03:00
rtl Rename folder structure and update hexdump generator 2022-11-28 06:52:08 +00:00
test Add unit tests 2022-11-28 03:07:21 -03:00
.gitignore Rename folder structure and update hexdump generator 2022-11-28 06:52:08 +00:00
README.md Update 'README.md' 2022-11-27 22:45:51 +00:00

README.md

5-Stage RISC-V pipelined processor with hazard detection