23 lines
482 B
Systemverilog
23 lines
482 B
Systemverilog
`timescale 1ns / 1ps
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module jump_control (
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input logic jump,
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input logic branch,
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input logic branch_alu_neg,
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input logic zero,
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output logic pc_src
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);
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logic alu_result, branch_result;
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assign alu_result = !zero;
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always_comb begin
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case (branch_alu_neg)
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'd0: branch_result = alu_result;
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'd1: branch_result = !alu_result;
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default: branch_result = 1'dx;
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endcase
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end
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assign pc_src = (branch & branch_result) | jump;
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endmodule
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