26 lines
485 B
Systemverilog
26 lines
485 B
Systemverilog
`timescale 1ns / 1ps
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module Test_ALU ();
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logic [31:0] a, b;
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logic [ 2:0] opcode;
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logic [31:0] result;
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logic [ 3:0] status;
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ALU alu (
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.a(a),
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.b(b),
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.opcode(opcode),
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.result(result),
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.status(status)
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);
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initial begin
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a = 'd3;
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b = 'd11;
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opcode = 'd0;
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assert(result != 'd14) $display("3 + 11 != 14");
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assert(status != 'b0000) $display("status(3 + 11) != 0000");
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$display("Test successful");
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$finish;
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end
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endmodule
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