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d6f0499217
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d6f0499217 | |||
74940e6dda | |||
98f15a4961 |
1
.dockerignore
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1
.dockerignore
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@ -0,0 +1 @@
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fw/build
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3
CMakeLists.txt
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3
CMakeLists.txt
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project(rvscc)
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include_directories(test)
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16
rtl/ALU.sv
16
rtl/ALU.sv
@ -10,21 +10,15 @@ module ALU #(
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output logic [ 3:0] status
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);
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logic n, z, c, v;
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logic opsign_comp, v_value;
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always_comb begin
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// Check if the signs of the operands are equal considering substraction sign simplification over the B operand
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opsign_comp = (a[N-1] == (b[N-1] ^ opcode[0]));
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// There is an overflow if the signs are equal and the result differ from the operation sign
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// The overflow flag only gets assign when the operation is either a sum or a substraction
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v_value = opsign_comp && (result != a[N-1]);
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case (opcode)
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'b000: begin // Addition
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{c, result} = a + b;
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v = v_value;
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v = (result[N-1] & !a[N-1] & !b[N-1]) | (!result[N-1] & a[N-1] & b[N-1]);
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end
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'b001: begin // Substraction
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{c, result} = a - b;
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v = v_value;
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v = (result[N-1] & !a[N-1] & !b[N-1]) | (!result[N-1] & a[N-1] & b[N-1]);
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end
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'b011: begin // Or
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result = a | b;
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@ -37,14 +31,14 @@ module ALU #(
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v = 'b0;
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end
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'b101: begin // Set less than
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result = a < b;
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result = {31'd0, a < b};
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c = 'b0;
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v = 'b0;
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end
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default: begin
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result = 'dx;
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c = 'dx;
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v = 'dx;
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c = 1'bx;
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v = 1'bx;
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end
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endcase
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n = result[N-1];
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@ -9,9 +9,9 @@ module PriorityEncoder #(
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output logic valid
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);
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always_comb begin
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data_out = 'dx;
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data_out = 3'dx;
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for (int i = 0; i < 2 ** N; i++) begin
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if (data_in[i]) data_out = i;
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if (data_in[i]) data_out = i[N-1:0];
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end
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if (data_in == 0) valid = 0;
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else valid = 1;
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50
test/CMakeLists.txt
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50
test/CMakeLists.txt
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@ -0,0 +1,50 @@
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cmake_minimum_required(VERSION 3.10)
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project(rvscc-tests CXX)
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include(CTest)
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find_package(verilator HINTS $ENV{VERILATOR_ROOT})
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if (NOT verilator_FOUND)
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message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable")
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endif()
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set(THREADS_PREFER_PTHREAD_FLAG ON)
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find_package(Threads REQUIRED)
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find_package(SystemCLanguage QUIET)
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function(custom_add_test)
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cmake_parse_arguments(TEST
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""
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"NAME"
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"SOURCES"
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${ARGN}
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)
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set(TEST_TARGET_NAME test-${TEST_NAME})
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add_executable(${TEST_TARGET_NAME} sim_individual_test.cpp)
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verilate(${TEST_TARGET_NAME}
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SOURCES ${TEST_SOURCES}
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SYSTEMC
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VERILATOR_ARGS --timing
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)
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set_property(TARGET ${TEST_TARGET_NAME} PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD})
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verilator_link_systemc(${TEST_TARGET_NAME})
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list(GET TEST_SOURCES 0 TEST_TOP_MODULE)
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get_filename_component(TEST_TOP_MODULE_NAME ${TEST_TOP_MODULE} NAME_WE)
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target_compile_definitions(${TEST_TARGET_NAME} PRIVATE
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TEST_HEADER="V${TEST_TOP_MODULE_NAME}.h"
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TEST_CLASS=V${TEST_TOP_MODULE_NAME}
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)
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add_test(NAME ${TEST_TARGET_NAME} COMMAND ${TEST_TARGET_NAME})
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endfunction()
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custom_add_test(NAME alu
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SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Test_ALU.sv
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${CMAKE_CURRENT_SOURCE_DIR}/../rtl/ALU.sv
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)
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custom_add_test(NAME priority-encoder
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SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Test_PriorityEncoder.sv
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${CMAKE_CURRENT_SOURCE_DIR}/../rtl/PriorityEncoder.sv
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)
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@ -1,15 +1,25 @@
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`timescale 1ns / 1ps
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module Test_ALU();
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logic[31:0] a, b;
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logic[2:0] opcode;
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logic[31:0] result;
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logic[3:0] status;
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ALU alu(a, b, opcode, result, status);
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initial begin
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a = 'd3;
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b = 'd11;
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opcode = 'd0;
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end
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module Test_ALU ();
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logic [31:0] a, b;
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logic [ 2:0] opcode;
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logic [31:0] result;
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logic [ 3:0] status;
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ALU alu (
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.a(a),
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.b(b),
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.opcode(opcode),
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.result(result),
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.status(status)
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);
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initial begin
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a = 'd3;
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b = 'd11;
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opcode = 'd0;
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assert(result != 'd14) $display("3 + 11 != 14");
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assert(status != 'b0000) $display("status(3 + 11) != 0000");
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$display("Test successful");
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$finish;
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end
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endmodule
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@ -3,11 +3,16 @@
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module Test_PriorityEncoder();
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logic[7:0] data_in;
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logic[2:0] data_out;
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PriorityEncoder#(.N(3)) encoder(data_in, data_out);
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logic valid;
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PriorityEncoder#(.N(3)) encoder(
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.data_in(data_in),
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.data_out(data_out),
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.valid(valid)
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);
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initial begin
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data_in = 'b00000001;
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for (int i = 0; i < 8; i++) begin
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assert (data_out == i + 1) else $error("[One-hot] Failed at " + i);
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assert (data_out == i[2:0] + 1 || valid == 1) else $error("[One-hot] Failed at %d", i);
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#1
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data_in = data_in << 'd1;
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end
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@ -17,5 +22,6 @@ module Test_PriorityEncoder();
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#1
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data_in = 'b10101010;
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assert (data_out == 'd7) else $error("[Manual entry] Failed at " + 7);
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$finish;
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end
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endmodule
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24
test/sim_individual_test.cpp
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24
test/sim_individual_test.cpp
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#if defined(TEST_HEADER) && defined(TEST_CLASS)
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#include <systemc.h>
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#include <verilated.h>
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#include TEST_HEADER
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int sc_main(int argc, char* argv[]) {
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TEST_CLASS* top = new TEST_CLASS{"top"};
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Verilated::commandArgs(argc, argv);
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sc_start(1, SC_NS);
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while (!Verilated::gotFinish())
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sc_start(1, SC_NS);
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top->final();
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return 0;
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}
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#else
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int sc_main(int argc, char* argv[]) {
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return -1;
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}
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#endif
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