This commit is contained in:
Mario Romero 2023-03-19 23:42:51 -03:00
commit d1bf9801a7

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@ -1,40 +1,48 @@
`timescale 1ns / 1ps `include "timescale.sv"
import rv32i_defs::*;
module test_two_way_lru_cache(); module test_two_way_lru_cache();
logic clk, rst;
logic[31:0] addr; logic clk, rst;
logic write_enable; data_memory_if mem_if(.clk(clk), .rst(rst));
logic[31:0] write_data;
logic[31:0] read_data; two_way_lru_cache DUT(
logic hit; .data_mem_if(mem_if)
);
TwoWayLRUCache #(
.ADDR_SIZE(32), localparam int ClockCycle = 2;
.NUM_SETS(16), always #(ClockCycle/2) clk = !clk;
.BLOCK_SIZE(32)
) cache ( localparam int MemoryWriteRange = 64;
clk, logic [MemoryWriteRange-1:0][OperandSize-1:0] write_values;
rst, int start_addr;
addr,
write_enable, initial begin
write_data, // Reset
read_data, clk = 0;
hit rst = 1;
); mem_if.write_enable = 0;
#4;
always #1 clk = ~clk; rst = 0;
initial begin // Write to a range of values in memory
clk = 0; mem_if.write_enable = 1;
rst = 1; start_addr = $urandom;
write_enable = 0; for (int i = 0; i < MemoryWriteRange; i++) begin
#2; mem_if.addr = 32'(start_addr + i * 4);
rst = 0; write_values[i] = $urandom;
#2; mem_if.write_data = write_values[i];
write_enable = 1; #2;
for(int i = 0; i < 64; i++) begin
addr = $urandom();
write_data = $urandom();
#2;
end
end end
// Read and compare the same range of values
mem_if.write_enable = 0;
#4;
for (int i = 0; i < MemoryWriteRange; i++) begin
mem_if.addr = 32'(start_addr + i * 4);
#2;
end
$finish;
end
endmodule endmodule