This commit is contained in:
Mario Romero 2023-03-19 23:42:51 -03:00
commit d1bf9801a7

View File

@ -1,40 +1,48 @@
`timescale 1ns / 1ps
`include "timescale.sv"
import rv32i_defs::*;
module test_two_way_lru_cache();
logic clk, rst;
logic[31:0] addr;
logic write_enable;
logic[31:0] write_data;
logic[31:0] read_data;
logic hit;
TwoWayLRUCache #(
.ADDR_SIZE(32),
.NUM_SETS(16),
.BLOCK_SIZE(32)
) cache (
clk,
rst,
addr,
write_enable,
write_data,
read_data,
hit
);
always #1 clk = ~clk;
initial begin
clk = 0;
rst = 1;
write_enable = 0;
#2;
rst = 0;
#2;
write_enable = 1;
for(int i = 0; i < 64; i++) begin
addr = $urandom();
write_data = $urandom();
#2;
end
logic clk, rst;
data_memory_if mem_if(.clk(clk), .rst(rst));
two_way_lru_cache DUT(
.data_mem_if(mem_if)
);
localparam int ClockCycle = 2;
always #(ClockCycle/2) clk = !clk;
localparam int MemoryWriteRange = 64;
logic [MemoryWriteRange-1:0][OperandSize-1:0] write_values;
int start_addr;
initial begin
// Reset
clk = 0;
rst = 1;
mem_if.write_enable = 0;
#4;
rst = 0;
// Write to a range of values in memory
mem_if.write_enable = 1;
start_addr = $urandom;
for (int i = 0; i < MemoryWriteRange; i++) begin
mem_if.addr = 32'(start_addr + i * 4);
write_values[i] = $urandom;
mem_if.write_data = write_values[i];
#2;
end
// Read and compare the same range of values
mem_if.write_enable = 0;
#4;
for (int i = 0; i < MemoryWriteRange; i++) begin
mem_if.addr = 32'(start_addr + i * 4);
#2;
end
$finish;
end
endmodule