Add tracing

test/CMakeLists.txt

@@ -20,14 +20,12 @@ function(rvscc_add_test)
     ${ARGN}
   )
   set(TEST_TARGET_NAME test-${TEST_NAME})
-  add_executable(${TEST_TARGET_NAME} sim_individual_test.cpp)
+  add_executable(${TEST_TARGET_NAME} sim_main.cpp)
   verilate(${TEST_TARGET_NAME}
     SOURCES ${TEST_SOURCES}
-    SYSTEMC
+	TRACE
     VERILATOR_ARGS --timing
   )
-  set_property(TARGET ${TEST_TARGET_NAME} PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD})
-  verilator_link_systemc(${TEST_TARGET_NAME})
   list(GET TEST_SOURCES 0 TEST_TOP_MODULE)
   get_filename_component(TEST_TOP_MODULE_NAME ${TEST_TOP_MODULE} NAME_WE)
   target_compile_definitions(${TEST_TARGET_NAME} PRIVATE

test/Test_DataMemory.sv

@@ -10,7 +10,7 @@ module Test_DataMemory ();
   localparam int MemorySize = 16;
   DataMemory #(
       .SIZE(MemorySize)
-  ) data_memory (
+  ) DUT (
       .clk(clk),
       .rst(rst),
       .addr(addr),
@@ -26,6 +26,8 @@ module Test_DataMemory ();
   logic [MemoryWriteRange:0][31:0] write_values;
   int start_addr;
   initial begin
+    $dumpfile("dump.vcd");
+    $dumpvars();
     // Reset
     clk = 0;
     rst = 1;
@@ -35,7 +37,7 @@ module Test_DataMemory ();
     #1;
     // Write to a range of values in memory
     write_enable = 1;
-    start_addr = $urandom_range(15);
+    start_addr   = $urandom_range(15);
     for (int i = 0; i < MemoryWriteRange; i++) begin
       addr = start_addr + i;
       write_values[i] = $urandom();

test/sim_individual_test.cpp

@@ -1,24 +0,0 @@
-#if defined(TEST_HEADER) && defined(TEST_CLASS)
-
-#include <systemc.h>
-#include <verilated.h>
-
-#include TEST_HEADER
-
-int sc_main(int argc, char* argv[]) {
-    TEST_CLASS* top = new TEST_CLASS{"top"};
-    Verilated::commandArgs(argc, argv);
-    sc_start(1, SC_NS);
-    while (!Verilated::gotFinish())
-        sc_start(1, SC_NS);
-    top->final();
-    return 0;
-}
-
-#else
-
-int sc_main(int argc, char* argv[]) {
-    return -1;
-}
-
-#endif

test/sim_main.cpp

@@ -0,0 +1,52 @@
+#include "verilated.h"
+
+/**
+ * \def TEST_HEADER
+ * \brief Verilator header file to be included
+ *
+ * \def TEST_CLASS
+ * \brief Verilator model class
+ */
+
+#if defined(TEST_HEADER) && defined(TEST_CLASS)
+
+#include TEST_HEADER
+
+#include <memory>
+
+int main(int argc, char** argv, char**) {
+    // Setup context, defaults, and parse command line
+    Verilated::debug(0);
+    const std::unique_ptr<VerilatedContext> context{new VerilatedContext};
+    context->traceEverOn(true);
+    context->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from TEST_HEADER generated from Verilating
+    const std::unique_ptr<TEST_CLASS> top{new TEST_CLASS{context.get()}};
+
+    // Simulate until $finish
+    while (!context->gotFinish()) {
+        // Evaluate model
+        top->eval();
+        // Advance time
+        if (!top->eventsPending()) break;
+        context->time(top->nextTimeSlot());
+    }
+
+    if (!context->gotFinish()) {
+        VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
+    }
+
+    // Final model cleanup
+    top->final();
+    return 0;
+}
+
+#else
+
+int main(int argc, char** argv, char**) {
+    VL_DEBUG_IF(VL_PRINTF("+ Undefined TEST_HEADER and TEST_CLASS\n"););
+	return -1;
+}
+
+#endif