Add Data Memory test

CMakeLists.txt

@@ -8,7 +8,7 @@ include(ExternalProject)
 ExternalProject_Add(firmware
   SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/fw
   BINARY_DIR ${CMAKE_CURRENT_SOURCE_DIR}/build/fw
-  CMAKE_ARGS -DCMAKE_TOOLCHAIN_FILE=${CMAKE_CURRENT_SOURCE_DIR}/fw/cmake/riscv-toolchain.cmake
+  CMAKE_ARGS -DCMAKE_TOOLCHAIN_FILE=${CMAKE_CURRENT_SOURCE_DIR}/cmake/riscv-toolchain.cmake
   INSTALL_COMMAND ""
 )
 

fw/cmake/riscv-toolchain.cmake

@@ -1,14 +0,0 @@
-set(CMAKE_SYSTEM_NAME Generic)
-
-find_program(RISCV_GCC_FOUND
-  NAMES riscv-none-elf-gcc riscv32-unknown-elf-gcc)
-
-get_filename_component(GCC_BIN ${RISCV_GCC_FOUND} NAME)
-
-string(REPLACE gcc "" TOOLCHAIN_PREFIX ${GCC_BIN})
-
-set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}as)
-set(CMAKE_C_COMPILER   ${TOOLCHAIN_PREFIX}gcc)
-set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++)
-set(CMAKE_OBJCOPY      ${TOOLCHAIN_PREFIX}objcopy)
-set(CMAKE_OBJDUMP      ${TOOLCHAIN_PREFIX}objdump)

fw/cmake/utils.cmake

@@ -1,31 +0,0 @@
-cmake_minimum_required(VERSION 3.10)
-
-function(rvscc_bin_to_verilog_mem_file)
-  cmake_parse_arguments(RVSCC
-    ""
-    "TARGET"
-    ""
-    ${ARGN}
-  )
-  add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
-        COMMAND ${CMAKE_OBJCOPY} -j .text
-            -O verilog
-            --verilog-data-width=1
-            --reverse-bytes=4
-            "$<TARGET_FILE:${RVSCC_TARGET}>" ${RVSCC_TARGET}.mem
-        COMMENT "Invoking: Verilog Hexdump"
-    )
-endfunction()
-
-function(rvscc_dissasemble)
-  cmake_parse_arguments(RVSCC
-    ""
-    "TARGET"
-    ""
-    ${ARGN}
-  )
-  add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
-    COMMAND ${CMAKE_OBJDUMP} -S "$<TARGET_FILE:${RVSCC_TARGET}>" > ${RVSCC_TARGET}.disasm
-          COMMENT "Invoking: Disassemble"
-  )
-endfunction()

fw/test/CMakeLists.txt

@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.10)
 
 project(test ASM)
-include(${CMAKE_CURRENT_SOURCE_DIR}/../cmake/utils.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../cmake/utils.cmake)
 
 option(DISSASEMBLY "Enable dissasembly" OFF)
 

rtl/DataMemory.sv

@@ -1,16 +1,16 @@
 `timescale 1ns / 1ps
 
 module DataMemory #(
-parameter N = 32,
-parameter SIZE = 32,
-parameter BYTE_WIDTH = 8)(
+parameter int N = 32,
+parameter int SIZE = 32,
+parameter int BYTE_WIDTH = 8)(
     input logic clk, rst,
     input logic[N-1:0] addr,
     input logic write_enable,
     input logic[N-1:0] write_data,
     output logic[N-1:0] read_data
 );
-    logic[BYTE_WIDTH-1:0] mem[SIZE*BYTE_WIDTH-1:0];
+    logic[SIZE*BYTE_WIDTH-1:0][BYTE_WIDTH-1:0] mem;
 
     assign read_data = {mem[addr + 'd0],
                         mem[addr + 'd1],
@@ -18,11 +18,11 @@ parameter BYTE_WIDTH = 8)(
                         mem[addr + 'd3]};
     always_ff @(posedge clk) begin
         if (rst)
-            mem = '{default: '0};
+            mem <= '{default: '0};
         else if (write_enable)
             {mem[addr + 'd0],
              mem[addr + 'd1],
              mem[addr + 'd2],
              mem[addr + 'd3]} <= write_data;
     end
-endmodule
+endmodule

test/CMakeLists.txt

@@ -12,7 +12,7 @@ find_package(Threads REQUIRED)
 
 find_package(SystemCLanguage QUIET)
 
-function(custom_add_test)
+function(rvscc_add_test)
   cmake_parse_arguments(TEST
     ""
     "NAME"
@@ -37,12 +37,17 @@ function(custom_add_test)
   add_test(NAME ${TEST_TARGET_NAME} COMMAND ${TEST_TARGET_NAME})
 endfunction()
 
-custom_add_test(NAME alu
+rvscc_add_test(NAME alu
   SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Test_ALU.sv
           ${CMAKE_CURRENT_SOURCE_DIR}/../rtl/ALU.sv
 )
 
-custom_add_test(NAME priority-encoder
+rvscc_add_test(NAME priority-encoder
   SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Test_PriorityEncoder.sv
           ${CMAKE_CURRENT_SOURCE_DIR}/../rtl/PriorityEncoder.sv
 )
+
+rvscc_add_test(NAME data-memory
+	SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Test_DataMemory.sv
+			${CMAKE_CURRENT_SOURCE_DIR}/../rtl/DataMemory.sv
+)

test/Test_DataMemory.sv

@@ -1,36 +1,54 @@
 `timescale 1ns / 1ps
 
-module Test_DataMemory();
-    logic clk, rst;
-    logic[31:0] addr;
-    logic write_enable;
-    logic[31:0] write_data;
-    logic[31:0] read_data;
-    
-    DataMemory #(
-        .SIZE(16)
-    ) data_memory(
-        clk,
-        rst,
-        addr,
-        write_enable,
-        write_data,
-        read_data
-    );
-    
-    always #1 clk = ~clk;
-    initial begin
-        clk = 0;
-        rst = 1;
-        write_enable = 0;
-        #4;
-        rst = 0;
-        #1;
-        write_enable = 1;
-        for(int i = 0; i < 16; i++) begin
-            addr = $urandom_range(15);
-            write_data = $urandom();
-            #2;
-        end
+module Test_DataMemory ();
+  logic clk, rst;
+  logic [31:0] addr;
+  logic write_enable;
+  logic [31:0] write_data;
+  logic [31:0] read_data;
+
+  localparam int MemorySize = 16;
+  DataMemory #(
+      .SIZE(MemorySize)
+  ) data_memory (
+      .clk(clk),
+      .rst(rst),
+      .addr(addr),
+      .write_enable(write_enable),
+      .write_data(write_data),
+      .read_data(read_data)
+  );
+
+  always #1 clk = ~clk;
+
+  localparam int MemoryWriteRange = 16;
+
+  logic [MemoryWriteRange:0][31:0] write_values;
+  int start_addr;
+  initial begin
+    // Reset
+    clk = 0;
+    rst = 1;
+    write_enable = 0;
+    #4;
+    rst = 0;
+    #1;
+    // Write to a range of values in memory
+    write_enable = 1;
+    start_addr = $urandom_range(15);
+    for (int i = 0; i < MemoryWriteRange; i++) begin
+      addr = start_addr + i;
+      write_values[i] = $urandom();
+      write_data = write_values[i];
+      #2;
     end
+    // Read and compare the same range of values
+    write_enable = 0;
+    for (int i = 0; i < 16; i++) begin
+      addr = start_addr + i;
+      assert (read_data == write_values[i])
+      else $error("Read failed at address %h", addr);
+    end
+    $finish;
+  end
 endmodule