Fix verilator test

rtl/cache_controller.sv

@@ -24,7 +24,7 @@ module cache_controller #(
 
   typedef struct packed {
     logic [TagSize - 1:0] tag;
-    logic [SetSize - 1:0] set;
+    logic [SetSize - 1:0] addr_set;
     logic [ByteOffsetSize - 1:0] byte_offset;
   } cache_addr_t;
 
@@ -39,14 +39,14 @@ module cache_controller #(
 
   always_comb begin
     packed_addr = cache_addr_t'(addr);
-    set = packed_addr.set;
+    set = packed_addr.addr_set;
     tag = packed_addr.tag;
 
-    state = cache_state_t'{write_enable, populated};
+    state = cache_state_t'({write_enable, populated});
     case (state)
       READ: begin
         cru_enable = 0;
-        write_way = 'dx;
+        write_way = 1'dx;
       end
       WRITE_POPULATE: begin
         cru_enable = 0;
@@ -58,7 +58,7 @@ module cache_controller #(
       end
       default: begin
         cru_enable = 0;
-        write_way = 'dx;
+        write_way = 1'dx;
       end
     endcase
   end

rtl/two_way_lru_cache.sv

@@ -18,9 +18,11 @@ module two_way_lru_cache #(
   logic read_valid;
 
   logic [WaySize - 1:0] way;
-  logic [SetSize - 1:0] set;
+  logic [SetSize - 1:0] xset;
   logic [TagSize - 1:0] tag;
 
+  logic write_way;
+  logic populated;
   cache_memory #(
       .ADDR_SIZE (ADDR_SIZE),
       .NUM_SETS  (NUM_SETS),
@@ -30,7 +32,7 @@ module two_way_lru_cache #(
       .clk(data_mem_if.clk),
       .rst(data_mem_if.rst),
       .write_way(write_way),
-      .set(set),
+      .set(xset),
       .tag(tag),
       .write_enable(data_mem_if.write_enable),
       .write_data(data_mem_if.write_data),
@@ -40,6 +42,8 @@ module two_way_lru_cache #(
       .hit(data_mem_if.hit)
   );
 
+  logic cru_enable;
+  logic replace_preferred_way;
   two_way_lru_cru #(
       .ADDR_SIZE (ADDR_SIZE),
       .NUM_SETS  (NUM_SETS),
@@ -65,7 +69,7 @@ module two_way_lru_cache #(
       .populated(populated),
       .cru_enable(cru_enable),
       .write_way(write_way),
-      .set(set),
+      .set(xset),
       .tag(tag)
   );
 endmodule

rtl/two_way_lru_cru.sv

@@ -18,7 +18,7 @@ module two_way_lru_cru #(
 
   typedef struct packed {
     logic [ByteOffsetSize - 1:0] byte_offset;
-    logic [SetSize - 1:0] set;
+    logic [SetSize - 1:0] xset;
     logic [TagSize - 1:0] tag;
   } cache_addr_t;
 
@@ -27,11 +27,11 @@ module two_way_lru_cru #(
 
   logic [NUM_SETS - 1:0] lru;
 
-  assign preferred = lru[packed_addr.set];
+  assign preferred = lru[packed_addr.xset];
   always_ff @(posedge clk) begin
     if (rst) lru <= 'd0;
     else if (replace) begin
-      lru[packed_addr.set] <= !lru[packed_addr.set];
+      lru[packed_addr.xset] <= !lru[packed_addr.xset];
     end
   end
 endmodule

test/CMakeLists.txt

@@ -50,8 +50,7 @@ rvscc_add_test(
 )
 
 rvscc_add_test(
-  NAME instruction_memory
-  TOP test_instr_memory
+  NAME instruction_memory TOP test_instr_memory
   SOURCES ${PROJECT_SOURCE_DIR}/rtl/rv32i_defs.sv
           ${PROJECT_SOURCE_DIR}/rtl/instr_memory_if.sv
           ${PROJECT_SOURCE_DIR}/rtl/instr_memory.sv
@@ -111,7 +110,9 @@ rvscc_add_test(
   	SOURCES ${PROJECT_SOURCE_DIR}/rtl/rv32i_defs.sv
 			${PROJECT_SOURCE_DIR}/rtl/two_way_lru_cache.sv
 			${PROJECT_SOURCE_DIR}/rtl/two_way_lru_cru.sv
+            ${PROJECT_SOURCE_DIR}/rtl/data_memory_if.sv
 			${PROJECT_SOURCE_DIR}/rtl/cache_memory.sv
+			${PROJECT_SOURCE_DIR}/rtl/cache_controller.sv
   			${PROJECT_SOURCE_DIR}/rtl/priority_encoder.sv
 	        ${PROJECT_SOURCE_DIR}/test/test_two_way_lru_cache.sv
 )