6 lines
265 B
Markdown
6 lines
265 B
Markdown
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---
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title: RVSCC: RISC-V 5-Stage Pipelined Processor
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category: projects
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---
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Pametrizable design of a processor implementing the RV32I ISA in SystemVerilog with an N-Way memory
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cache using CMake integration for instruction loading in C or RISC-V Assembly.
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