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c82235a2de
git-svn-id: file://localhost/svn/verilator/trunk/verilator@767 77ca24e4-aefa-0310-84f0-b9a241c72d87
118 lines
2.5 KiB
Verilog
118 lines
2.5 KiB
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk, fastclk, reset_l
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);
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input clk /*verilator sc_clock*/;
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input fastclk /*verilator sc_clock*/;
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input reset_l;
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output passed;
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// Combine passed signals from each sub signal
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// verilator lint_off MULTIDRIVEN
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wire [20:0] passedv;
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// verilator lint_on MULTIDRIVEN
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wire passed = &passedv;
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t_arith tarith
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(.passed (passedv[0]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_case tcase
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(.passed (passedv[1]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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assign passedv[2] = 1'b1;
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t_equal tequal
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(.passed (passedv[3]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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assign passedv[4] = 1'b1;
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t_initial tinitial
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(.passed (passedv[5]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_inst tinst
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(.passed (passedv[6]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.fastclk (fastclk));
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t_param tparam
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(.passed (passedv[7]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_rnd trnd
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(.passed (passedv[8]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_mem tmem
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(.passed (passedv[9]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_blocking tblocking
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(.passed (passedv[10]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.reset_l (reset_l));
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t_clk tclk
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(.passed (passedv[11]),
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/*AUTOINST*/
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// Inputs
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.fastclk (fastclk),
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.clk (clk),
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.reset_l (reset_l));
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assign passedv[12] = 1'b1;
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t_func tfunc
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(.passed (passedv[13]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_chg tchg
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(.passed (passedv[14]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.fastclk (fastclk));
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t_loop tloop
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(.passed (passedv[15]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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assign passedv[16] = 1'b1;
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assign passedv[17] = 1'b1;
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assign passedv[18] = 1'b1;
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t_task ttask
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(.passed (passedv[19]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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t_netlist tnetlist
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(.passed (passedv[20]),
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.also_fastclk (fastclk),
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/*AUTOINST*/
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// Inputs
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.fastclk (fastclk));
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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