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20 lines
449 B
Systemverilog
20 lines
449 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Make sure type errors aren't suppressable
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// verilator lint_off WIDTH
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module t(/*AUTOARG*/);
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bit bad_parent;
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sub sub
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(.bad_sub_ref(bad_parent)); // Type mismatch
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endmodule
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module sub(ref real bad_sub_ref);
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endmodule
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