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d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
38 lines
1.0 KiB
Systemverilog
38 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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timeunit 1ns;
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timeprecision 1ps;
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time t;
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initial begin
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t = 10ns;
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$write("[%0t] In %m: Hi\n", $time);
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$printtimescale;
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 0, "-my-ms", 8);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 1, "-my-ms", 10);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-6, 2, "-my-us", 12);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-9, 3, "-my-ns", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-12, 3, "-my-ps", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-15, 4, "-my-fs", 14);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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