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19 lines
318 B
Systemverilog
19 lines
318 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module a();
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endmodule
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module test();
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a a();
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endmodule
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module a();
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endmodule
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module b();
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endmodule
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