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44 lines
745 B
Systemverilog
44 lines
745 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(/*AUTOARG*/);
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event ev_test;
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int i;
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bit toggle = 1'b0;
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bit clk;
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always #10 clk = ~clk;
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initial begin
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@(posedge clk);
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@(ev_test);
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toggle = ~toggle;
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end
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initial begin
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars(0, top);
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for(i=0; i < 10; i++) begin
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@(posedge clk);
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if (i == 5)
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->ev_test;
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end
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@(posedge clk);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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