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20 lines
525 B
Systemverilog
20 lines
525 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t;
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integer fd, cnt;
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initial begin
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fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/zeros.log"}, "w");
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for (cnt = 0; cnt < 16; cnt = cnt + 4)
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$fwrite(fd, "%u", 32'd0);
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$fclose(fd);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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