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47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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parameter string ES = "";
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parameter EI = ""; // B is an integer of width 8
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parameter string OS = "O";
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parameter OI = "O"; // B is an integer of width 8
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parameter bit [31:0] NEST = "NEST";
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parameter bit [31:0] TEST = "TEST";
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bit [31:0] rest;
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string s;
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initial begin
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$display(">< == >%s<", "");
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$display(">< == >%s<", ES);
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$display("> < == >%s<", EI);
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if ($bits("") != 0) $stop;
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if ($bits("A") != 8) $stop;
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if ($bits(ES) != 0) $stop;
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if ($bits(EI) != 8) $stop;
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if ($bits(OS) != 8) $stop;
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if ($bits(OI) != 8) $stop;
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if (ES == "TEST") $stop; // Illegal in some simulators as not both strings
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if (EI == "TEST") $stop;
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if (OS == "TEST") $stop; // Illegal in some simulators as not both strings
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// verilator lint_off WIDTH
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if (OI == "TEST") $stop;
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if (rest == "TEST") $stop;
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if (ES == TEST) $stop;
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if (EI == TEST) $stop;
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if (OS == TEST) $stop;
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if (OI == TEST) $stop;
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if (rest == TEST) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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