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This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
235 lines
4.5 KiB
Plaintext
235 lines
4.5 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Sun May 8 19:00:32 2022 $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 $ clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
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$var wire 1 $ clk $end
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$var wire 32 % cyc [31:0] $end
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$var wire 8 E unpacked_array[-1] [7:0] $end
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$var wire 8 D unpacked_array[-2] [7:0] $end
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$var wire 8 F unpacked_array[0] [7:0] $end
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$var real 64 2 v_arr_real[0] $end
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$var real 64 4 v_arr_real[1] $end
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$var wire 2 ) v_arrp [2:1] $end
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$var wire 4 * v_arrp_arrp [3:0] $end
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$var wire 4 + v_arrp_strp [3:0] $end
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$var wire 1 > v_arru[1] $end
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$var wire 1 ? v_arru[2] $end
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$var wire 2 , v_arru_arrp[3] [2:1] $end
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$var wire 2 - v_arru_arrp[4] [2:1] $end
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$var wire 1 @ v_arru_arru[3][1] $end
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$var wire 1 A v_arru_arru[3][2] $end
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$var wire 1 B v_arru_arru[4][1] $end
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$var wire 1 C v_arru_arru[4][2] $end
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$var wire 2 . v_arru_strp[3] [1:0] $end
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$var wire 2 / v_arru_strp[4] [1:0] $end
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$var wire 3 : v_enumb [2:0] $end
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$var wire 6 ; v_enumb2_str [5:0] $end
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$var wire 32 8 v_enumed [31:0] $end
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$var wire 32 9 v_enumed2 [31:0] $end
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$var real 64 0 v_real $end
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$var wire 64 6 v_str32x2 [63:0] $end
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$var wire 2 & v_strp [1:0] $end
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$var wire 4 ' v_strp_strp [3:0] $end
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$var wire 2 ( v_unip_strp [1:0] $end
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$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
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$var wire 32 H PARAM [31:0] $end
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$upscope $end
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$scope module p2 $end
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$var wire 32 I PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 J PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 < b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 = a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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