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b08c694cd6
* Add a test to reproduce bug3182. Run the same HDL with -Oo to confirm the result is same. * Hopefully fix #3182. The result can be 0 only when polarity is true (no AstNot is found during traversal).
25 lines
798 B
Perl
Executable File
25 lines
798 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_const_opt.v");
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# Run the same design as t_const_opt.pl without bitopt tree optimization to make sure that the result is same.
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compile(
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verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "-Oo", "$Self->{t_dir}/t_const_opt.cpp"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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