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38 lines
887 B
Systemverilog
38 lines
887 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int imembera;
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function int inc_methoda; imembera += 1; return imembera; endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c1;
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Cls c2;
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Cls c3;
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c1 = new;
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c1.imembera = 10;
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if (c1.inc_methoda() != 11) $stop;
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// Assignment
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c2 = c1;
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if (c1.inc_methoda() != 12) $stop;
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if (c2.inc_methoda() != 13) $stop;
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if (c1.inc_methoda() != 14) $stop;
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// Shallow copy
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c3 = new c1;
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if (c1.inc_methoda() != 15) $stop;
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if (c3.inc_methoda() != 15) $stop;
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if (c1.inc_methoda() != 16) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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