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98 lines
2.2 KiB
Systemverilog
98 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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parameter [0:7] P = 8'd10
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)(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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localparam [0:7] Q = 8'd20;
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logic [ 0: 0] v_a = '0;
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logic [ 0: 1] v_b = '0;
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logic [ 0: 7] v_c = '0;
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logic [ 0: 8] v_d = '0;
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logic [ 0: 15] v_e = '0;
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logic [ 0: 16] v_f = '0;
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logic [ 0: 31] v_g = '0;
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logic [ 0: 32] v_h = '0;
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logic [ 0: 63] v_i = '0;
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logic [ 0: 64] v_j = '0;
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logic [ 0:127] v_k = '0;
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logic [ 0:128] v_l = '0;
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logic [ 0:255] v_m = '0;
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logic [ 0:256] v_n = '0;
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logic [ 0:511] v_o = '0;
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logic [ -1: 1] v_p = '0;
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logic [ -7: 7] v_q = '0;
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logic [ -15: 15] v_r = '0;
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logic [ -31: 31] v_s = '0;
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logic [ -63: 63] v_t = '0;
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logic [-127:127] v_u = '0;
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logic [-255:255] v_v = '0;
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always @(posedge clk) begin
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if (cyc == 0) begin
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v_a <= '1;
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v_b <= '1;
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v_c <= '1;
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v_d <= '1;
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v_e <= '1;
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v_f <= '1;
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v_g <= '1;
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v_h <= '1;
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v_i <= '1;
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v_j <= '1;
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v_k <= '1;
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v_l <= '1;
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v_m <= '1;
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v_n <= '1;
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v_o <= '1;
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v_p <= '1;
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v_q <= '1;
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v_r <= '1;
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v_s <= '1;
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v_t <= '1;
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v_u <= '1;
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v_v <= '1;
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end else begin
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v_a <= v_a << 1;
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v_b <= v_b << 1;
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v_c <= v_c << 1;
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v_d <= v_d << 1;
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v_e <= v_e << 1;
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v_f <= v_f << 1;
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v_g <= v_g << 1;
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v_h <= v_h << 1;
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v_i <= v_i << 1;
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v_j <= v_j << 1;
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v_k <= v_k << 1;
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v_l <= v_l << 1;
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v_m <= v_m << 1;
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v_n <= v_n << 1;
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v_o <= v_o << 1;
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v_p <= v_p << 1;
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v_q <= v_q << 1;
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v_r <= v_r << 1;
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v_s <= v_s << 1;
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v_t <= v_t << 1;
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v_u <= v_u << 1;
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v_v <= v_v << 1;
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end
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cyc <= cyc + 1;
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if (cyc == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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