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37 lines
864 B
Systemverilog
37 lines
864 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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let P = 11;
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endpackage
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module t(/*AUTOARG*/);
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let A = 10;
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let B() = 20;
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let C(a) = 30 + a;
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let D(a, b) = 30 + a + b;
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let E(a, b=7) = 30 + a + b;
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let F(untyped a) = 30 + a;
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let G(int a) = 30 + a;
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initial begin
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if (A != 10) $stop;
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if (A() != 10) $stop;
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if (B != 20) $stop;
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if (B() != 20) $stop;
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if (C(1) != (30 + 1)) $stop;
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if (D(1, 2) != (30 + 1 + 2)) $stop;
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if (E(1) != (30 + 1 + 7)) $stop;
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if (F(1) != (30 + 1)) $stop;
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if (G(1) != (30 + 1)) $stop;
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if (Pkg::P != 11) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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