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29 lines
542 B
Verilog
29 lines
542 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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interface intf;
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logic a;
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modport source(output a);
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modport sink(input a);
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endinterface
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module t
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#(
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parameter N = 1
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)
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( input [N-1:0] a_in,
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output[N-1:0] a_out
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);
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intf ifs[N-1:0] ();
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logic [N-1:0] a_q;
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assign a_out = a_q;
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assign ifs[0].a = a_in[0];
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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