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137 lines
2.7 KiB
Verilog
137 lines
2.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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`begin_keywords "VAMS-2.3"
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module t (/*autoarg*/
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// Inputs
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clk, in
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);
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input clk;
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input [15:0] in;
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wreal aout;
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integer cyc=0;
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real vin;
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wreal vpass;
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through through (.vin, .vpass);
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real gnd;
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wire out;
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within_range within_range (/*AUTOINST*/
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// Interfaces
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.vpass (vpass),
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.gnd (gnd),
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// Outputs
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.out (out));
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// wreal bus declaration
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wreal vin_upper_bus[1:0];
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// wreal nets declaration
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wreal vout_split_0;
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wreal vout_split_1;
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wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]),
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.vout_split_0(vout_split_0),
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.vout_split_1(vout_split_1));
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// implicit declaration of wreal
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`ifdef VERILATOR
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wreal wreal_implicit_net; // implicit declaration of wreal not supported yet
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`endif
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// verilator lint_off IMPLICIT
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first_level first_level(.in(cyc[0]), .out(wreal_implicit_net));
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// verilator lint_on IMPLICIT
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parameter real lsb = 1;
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// verilator lint_off WIDTH
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assign aout = $itor(in) * lsb;
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// verilator lint_on WIDTH
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n",$time, cyc, out, vin, gnd, within_range.in_int);
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`endif
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if (cyc==0) begin
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// Setup
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gnd = 0.0;
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vin = 0.2;
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end
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else if (cyc==2) begin
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if (out != 0) $stop;
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end
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else if (cyc==3) begin
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gnd = 0.0;
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vin = 0.6;
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end
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else if (cyc==4) begin
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if (out != 1) $stop;
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end
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else if (cyc==5) begin
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gnd = 0.6;
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vin = 0.8;
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end
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else if (cyc==6) begin
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if (out != 0) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module through
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(input wreal vin,
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output wreal vpass);
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assign vpass = vin;
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endmodule
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module within_range
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(input wreal vpass,
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input wreal gnd,
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output out);
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parameter real V_MIN = 0.5;
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parameter real V_MAX = 10;
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wreal in_int = vpass - gnd;
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wire out = (V_MIN <= in_int && in_int <= V_MAX);
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endmodule
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module wreal_bus
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(input wreal vin_bus [1:0],
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output wreal vout_split_0,
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output wreal vout_split_1);
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assign vout_split_0 = vin_bus[0];
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assign vout_split_1 = vin_bus[1];
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endmodule
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module first_level
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(input in,
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`ifdef VERILATOR
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output wreal out
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`else
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output out // Implicity becomes real
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`endif
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);
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second_level second_level(.in(in), .out(out));
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endmodule
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module second_level
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(input in,
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output out);
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wreal out;
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assign out = in ? 1.23456: 7.8910;
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endmodule
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