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20 lines
384 B
Verilog
20 lines
384 B
Verilog
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder
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module t (clk);
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input clk;
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tri [3:0] w;
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pullup p0 (w[0]);
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pulldown p1 (w[1]);
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pulldown p2 (w[2]);
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pullup p3 (w[3]);
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always_ff @ (posedge clk) begin
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if (w != 4'b1001) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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