verilator/test_regress/t/t_trace_cat_renew_0000.out
2018-08-30 20:05:13 -04:00

266 lines
2.7 KiB
Plaintext

$version Generated by VerilatedVcd $end
$date Thu Aug 30 16:11:06 2018
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 $ clk $end
$scope module t $end
$var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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b00000000000000000000000000000000 #
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