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37 lines
803 B
Verilog
37 lines
803 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t;
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reg [31:0] lastrand;
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reg [31:0] thisrand;
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integer same = 0;
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integer i;
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`define TRIES 20
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initial begin
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// There's a 1^32 chance of the numbers being the same twice,
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// so we'll allow one failure
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lastrand = $random;
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for (i=0; i<`TRIES; i=i+1) begin
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thisrand = $random;
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`ifdef TEST_VERBOSE
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$write("Random = %x\n", thisrand);
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`endif
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if (thisrand == lastrand) same=same+1;
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lastrand = thisrand;
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end
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if (same > 1) begin
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$write("%%Error: Too many similar numbers: %d\n", same);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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