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15 lines
312 B
Verilog
15 lines
312 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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module t (d, clk);
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input d;
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input clk;
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always @ (posedge clk) begin
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// Unsupported
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if ($past(d, 0, 0, 0)) $stop;
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end
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endmodule
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