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23 lines
468 B
Verilog
23 lines
468 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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// bug474
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package verb_pkg;
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typedef enum int {VERB_I,
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VERB_W} Verb_t;
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Verb_t verb = VERB_I;
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string message = " ";
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endpackage
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module t;
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import verb_pkg::*;
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string message = "*x*";
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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