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11 lines
217 B
Verilog
11 lines
217 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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//bug 1381
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logic root_var;
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// No module statements....
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