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17 lines
367 B
Verilog
17 lines
367 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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// verilator lint_off UNDRIVEN
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module t();
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wire sig;
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sub sub0(.out(33'b0));
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sub sub1(.out({32'b0, sig}));
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sub sub2(.out({32'b1, sig}));
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endmodule
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module sub(output reg [32 : 0] out);
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endmodule
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