verilator/test_regress/t/t_lint_realcvt_bad.v
2011-07-24 15:01:51 -04:00

12 lines
236 B
Verilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module sub;
integer i;
initial begin
i = 23.2;
end
endmodule