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33 lines
651 B
Verilog
33 lines
651 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// bug998
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module t1(input logic foo);
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initial begin
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$display("%m %d", foo);
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end
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endmodule
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module t();
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logic [1:0] my_foo;
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generate
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genvar the_genvar;
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for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
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//logic tmp_foo;
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//assign tmp_foo = my_foo[the_genvar];
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t1 t (.foo(my_foo[the_genvar]));
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//t1 t (.foo(tmp_foo));
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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