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54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Demonstrate deferred linking error messages
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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interface foo_intf;
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logic a;
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endinterface
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function integer the_other_func (input integer val);
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return val;
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endfunction
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module t (/*AUTOARG*/);
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localparam N = 4;
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foo_intf foos [N-1:0] ();
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logic [ 7 : 0 ] bar;
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// Non-constant dotted select is not allowed
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assign foos[bar].a = 1'b1;
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baz baz_inst ();
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// Unsure how to produce V3Param AstCellRef visitor errors
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//assign baz_inst.x = 1'b1;
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//assign baz_inst.N = 1'b1;
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//assign baz_inst.7 = 1'b1;
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//assign baz_inst.qux_t = 1'b1;
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//assign baz_inst.the_func = 1'b1;
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//assign baz_inst.the_lp = 1'b1;
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//assign bar.x = 1'b1;
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//assign fake_inst.x = 1'b1;
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//assign the_other_func.x = 1'b1;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module baz;
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typedef integer qux_t;
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function integer the_func (input integer val);
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return val;
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endfunction
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localparam the_lp = 5;
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endmodule
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