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20 lines
317 B
Verilog
20 lines
317 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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looped looped ();
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endmodule
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module looped (/*AUTOARG*/);
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looped looped ();
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endmodule
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