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33 lines
1.1 KiB
Verilog
33 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// simplistic example, should choose 1st conditional generate and assign straight through
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// the tool also compiles the special case and determines an error (replication value is 0)
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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`timescale 1ns / 1ps
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module t(data_i, data_o, single);
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parameter op_bits = 32;
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input [op_bits -1:0] data_i;
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output [31:0] data_o;
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input single;
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//simplistic example, should choose 1st conditional generate and assign straight through
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//the tool also compiles the special case and determines an error (replication value is 0
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generate
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if (op_bits == 32) begin : general_case
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assign data_o = data_i;
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// Test implicit signals
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/* verilator lint_off IMPLICIT */
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assign imp = single;
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/* verilator lint_on IMPLICIT */
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end
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else begin : special_case
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assign data_o = {{(32 -op_bits){1'b0}},data_i};
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/* verilator lint_off IMPLICIT */
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assign imp = single;
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/* verilator lint_on IMPLICIT */
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end
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endgenerate
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endmodule
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