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30 lines
817 B
Verilog
30 lines
817 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t ();
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parameter MSG_PORT_WIDTH = 4350;
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localparam PAYLOAD_MAX_BITS = 4352;
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reg [MSG_PORT_WIDTH-1:0] msg;
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initial begin
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// Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits.
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// verilator lint_off WIDTH
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func(msg);
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// verilator lint_on WIDTH
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if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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function integer func (output bit [PAYLOAD_MAX_BITS-1:0] data);
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/*verilator no_inline_task*/
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data = {PAYLOAD_MAX_BITS{1'b1}};
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return (1);
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endfunction
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endmodule
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