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62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder
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`define STRINGIFY(x) `"x`"
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module t;
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initial begin
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`ifdef D1A
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if (`STRINGIFY(`D4B) !== "") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D2A
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if (`STRINGIFY(`D2A) !== "VALA") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D3A
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if (`STRINGIFY(`D4B) !== "") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D3B
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if (`STRINGIFY(`D4B) !== "") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D4A
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if (`STRINGIFY(`D4A) !== "VALA") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D4B
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if (`STRINGIFY(`D4B) !== "") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D5A
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if (`STRINGIFY(`D5A) !== "VALA") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef D5A
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if (`STRINGIFY(`D5B) !== "VALB") $stop;
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`else
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$write("%%Error: Missing define\n"); $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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