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68 lines
2.0 KiB
Verilog
68 lines
2.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t;
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typedef logic [3:0] mc_t;
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typedef mc_t tocast_t;
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typedef struct packed {
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logic [15:0] data;
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} packed_t;
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packed_t pdata;
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assign pdata.data = 16'h1234;
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logic [7:0] logic8bit;
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assign logic8bit = $bits(logic8bit)'(pdata >> 8);
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mc_t o;
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logic [15:0] allones = 16'hffff;
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parameter FOUR = 4;
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// bug925
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localparam [6:0] RESULT = 7'((6*9+92)%96);
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logic signed [14:0] samp0 = 15'h0000;
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logic signed [14:0] samp1 = 15'h0000;
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logic signed [14:0] samp2 = 15'h6000;
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logic signed [11:0] coeff0 = 12'h009;
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logic signed [11:0] coeff1 = 12'h280;
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logic signed [11:0] coeff2 = 12'h4C5;
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logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11));
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// verilator lint_off WIDTH
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logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
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// verilator lint_on WIDTH
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logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
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(27'(coeff1 * samp1) >>> 11) +
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(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
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initial begin
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if (logic8bit != 8'h12) $stop;
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if (4'shf > 4'sh0) $stop;
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if (signed'(4'hf) > 4'sh0) $stop;
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if (4'hf < 4'h0) $stop;
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if (unsigned'(4'shf) < 4'h0) $stop;
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if (4'(allones) !== 4'hf) $stop;
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if (6'(allones) !== 6'h3f) $stop;
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if ((4)'(allones) !== 4'hf) $stop;
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if ((4+2)'(allones) !== 6'h3f) $stop;
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if ((4-2)'(allones) !== 2'h3) $stop;
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if ((FOUR+2)'(allones) !== 6'h3f) $stop;
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if (50 !== RESULT) $stop;
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o = tocast_t'(4'b1);
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if (o != 4'b1) $stop;
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if (15'h6cec != outa) $stop;
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if (27'h7ffecec != mida) $stop;
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if (27'h7ffecec != midb) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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