mirror of
https://github.com/verilator/verilator.git
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80 lines
3.5 KiB
XML
80 lines
3.5 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="AstRoot" language="1800-2017"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
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<file id="d" filename="input.vc" language="1800-2017"/>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="e6" name="t" submodname="t" hier="t">
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<cell fl="e18" name="cell1" submodname="mod1" hier="t.cell1"/>
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<cell fl="e24" name="cell2" submodname="mod2" hier="t.cell2"/>
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</cell>
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</cells>
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<netlist>
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<module fl="e6" name="t" origName="t" topModule="1">
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<var fl="e12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="e16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="e18" name="cell1" defName="mod1" origName="cell1">
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<port fl="e18" name="q" direction="out" portIndex="1">
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<varref fl="e18" name="between" dtype_id="2"/>
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</port>
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<port fl="e21" name="clk" direction="in" portIndex="2">
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<varref fl="e21" name="clk" dtype_id="1"/>
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</port>
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<port fl="e22" name="d" direction="in" portIndex="3">
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<varref fl="e22" name="d" dtype_id="2"/>
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</port>
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</instance>
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<instance fl="e24" name="cell2" defName="mod2" origName="cell2">
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<port fl="e24" name="d" direction="in" portIndex="1">
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<varref fl="e24" name="between" dtype_id="2"/>
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</port>
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<port fl="e27" name="q" direction="out" portIndex="2">
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<varref fl="e27" name="q" dtype_id="2"/>
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</port>
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<port fl="e29" name="clk" direction="in" portIndex="3">
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<varref fl="e29" name="clk" dtype_id="1"/>
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</port>
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</instance>
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</module>
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<module fl="e33" name="mod1" origName="mod1">
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<var fl="e35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<always fl="e39">
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<sentree fl="e39">
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<senitem fl="e39" edgeType="POS">
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<varref fl="e39" name="clk" dtype_id="1"/>
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</senitem>
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</sentree>
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<assigndly fl="e40" dtype_id="2">
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<varref fl="e40" name="d" dtype_id="2"/>
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<varref fl="e40" name="q" dtype_id="2"/>
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</assigndly>
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</always>
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</module>
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<module fl="e44" name="mod2" origName="mod2">
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<var fl="e46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="e51" dtype_id="2">
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<varref fl="e51" name="d" dtype_id="2"/>
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<varref fl="e51" name="q" dtype_id="2"/>
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</contassign>
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</module>
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<typetable fl="a0">
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<basicdtype fl="e46" id="1" name="logic"/>
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<basicdtype fl="e13" id="2" name="logic" left="3" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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