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15 lines
265 B
Verilog
15 lines
265 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire w;
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reg r;
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assign r = 1'b1;
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always @ (r) w = 1'b0;
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endmodule
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