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59 lines
1.3 KiB
Verilog
59 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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`ifdef USE_VPI_NOT_DPI
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//We call it via $c so we can verify DPI isn't required - see bug572
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`else
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import "DPI-C" context function integer mon_check();
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`endif
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */;
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integer i, status;
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// Test loop
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initial begin
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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`ifdef iverilog
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status = $mon_check();
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`endif
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`ifndef USE_VPI_NOT_DPI
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status = mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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for (i = 16; i > 0; i--)
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if (mem0[i] !== i) begin
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$write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i);
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status = 1;
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end
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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