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70 lines
1.7 KiB
Verilog
70 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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function int f_no_no ();
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int st = 2; st++; return st;
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endfunction
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function int f_no_st ();
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static int st = 2; st++; return st;
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endfunction
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function int f_no_au ();
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automatic int st = 2; st++; return st;
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endfunction
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function static int f_st_no ();
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int st = 2; st++; return st;
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endfunction
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function static int f_st_st ();
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static int st = 2; st++; return st;
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endfunction
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function static int f_st_au ();
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automatic int st = 2; st++; return st;
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endfunction
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function automatic int f_au_no ();
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int st = 2; st++; return st;
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endfunction
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function automatic int f_au_st ();
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static int st = 2; st++; return st;
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endfunction
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function automatic int f_au_au ();
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automatic int st = 2; st++; return st;
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endfunction
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initial begin
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if (f_no_no() != 3) $stop;
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if (f_no_no() != 4) $stop;
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if (f_no_st() != 3) $stop;
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if (f_no_st() != 4) $stop;
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if (f_no_au() != 3) $stop;
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if (f_no_au() != 3) $stop;
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//
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if (f_st_no() != 3) $stop;
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if (f_st_no() != 4) $stop;
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if (f_st_st() != 3) $stop;
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if (f_st_st() != 4) $stop;
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if (f_st_au() != 3) $stop;
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if (f_st_au() != 3) $stop;
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//
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if (f_au_no() != 3) $stop;
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if (f_au_no() != 3) $stop;
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if (f_au_st() != 3) $stop;
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if (f_au_st() != 4) $stop;
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if (f_au_au() != 3) $stop;
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if (f_au_au() != 3) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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