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33 lines
748 B
Verilog
33 lines
748 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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// see bug491
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package functions;
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function real abs (real num);
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abs = (num <0) ? -num : num;
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endfunction
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function real neg (real num);
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return -abs(num); // Check package funcs can call package funcs
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endfunction
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endpackage
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module t ();
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import functions::*;
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localparam P = 1;
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generate
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if (P == 1) begin
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initial begin
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if (abs(-2.1) != 2.1) $stop;
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if (abs(2.2) != 2.2) $stop;
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if (neg(-2.1) != -2.1) $stop;
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if (neg(2.2) != -2.2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endgenerate
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endmodule
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