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99 lines
2.1 KiB
Verilog
99 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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rst_sync_l, rst_both_l, rst_async_l, d, clk
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input clk; // To sub1 of sub1.v, ...
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input d; // To sub1 of sub1.v, ...
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input rst_async_l; // To sub2 of sub2.v
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input rst_both_l; // To sub1 of sub1.v, ...
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input rst_sync_l; // To sub1 of sub1.v
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// End of automatics
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sub1 sub1 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.rst_both_l (rst_both_l),
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.rst_sync_l (rst_sync_l),
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.d (d));
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sub2 sub2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.rst_both_l (rst_both_l),
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.rst_async_l (rst_async_l),
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.d (d));
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endmodule
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module sub1 (/*AUTOARG*/
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// Inputs
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clk, rst_both_l, rst_sync_l, d
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);
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input clk;
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input rst_both_l;
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input rst_sync_l;
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//input rst_async_l;
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input d;
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reg q1;
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reg q2;
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always @(posedge clk) begin
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if (~rst_sync_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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q1 <= 1'h0;
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// End of automatics
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end else begin
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q1 <= d;
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end
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end
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always @(posedge clk) begin
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q2 <= (~rst_both_l) ? 1'b0 : d;
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if (0 && q1 && q2) ;
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end
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endmodule
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module sub2 (/*AUTOARG*/
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// Inputs
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clk, rst_both_l, rst_async_l, d
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);
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input clk;
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input rst_both_l;
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//input rst_sync_l;
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input rst_async_l;
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input d;
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reg q1;
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reg q2;
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reg q3;
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always @(posedge clk or negedge rst_async_l) begin
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if (~rst_async_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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q1 <= 1'h0;
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// End of automatics
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end else begin
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q1 <= d;
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end
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end
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always @(posedge clk or negedge rst_both_l) begin
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q2 <= (~rst_both_l) ? 1'b0 : d;
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end
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// Make there be more async uses than sync uses
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always @(posedge clk or negedge rst_both_l) begin
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q3 <= (~rst_both_l) ? 1'b0 : d;
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if (0 && q1 && q2 && q3) ;
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end
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endmodule
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