mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
15 lines
276 B
Verilog
15 lines
276 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2017 by Wilson Snyder.
|
|
|
|
module t (/*AUTOARG*/
|
|
// Outputs
|
|
z
|
|
);
|
|
|
|
reg [3:0] r = 4'b1010;
|
|
output [2:1] z = r[2 :+ 1];
|
|
|
|
endmodule
|