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79 lines
1.6 KiB
Verilog
79 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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// This test demonstrates how not only parameters but the type of a parent
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// interface could propagate down to child modules, changing their data type
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// determinations. Note presently unsupported in all commercial simulators.
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interface ifc;
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parameter MODE = 0;
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generate
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// Note block must be named per SystemVerilog 2005
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if (MODE==1) begin : g
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integer value;
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end
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else if (MODE==2) begin : g
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real value;
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end
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endgenerate
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc #(1) itop1a();
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ifc #(1) itop1b();
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ifc #(2) itop2a();
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ifc #(2) itop2b();
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wrapper c1 (.isuba(itop1a),
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.isubb(itop1b),
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.i_valuea(14.1),
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.i_valueb(15.2));
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wrapper c2 (.isuba(itop2a),
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.isubb(itop2b),
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.i_valuea(24.3),
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.i_valueb(25.4));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==20) begin
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if (itop1a.g.value != 14) $stop;
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if (itop1b.g.value != 15) $stop;
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if (itop2a.g.value != 24) $stop;
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if (itop2b.g.value != 25) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module wrapper
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(
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ifc isuba,
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ifc isubb,
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input real i_valuea,
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input real i_valueb
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);
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lower subsuba (.isub(isuba), .i_value(i_valuea));
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lower subsubb (.isub(isubb), .i_value(i_valueb));
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endmodule
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module lower
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(
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ifc isub,
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input real i_value
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);
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always @* begin
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`error Commercial sims choke on cross ref here
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isub.g.value = i_value;
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end
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endmodule
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