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36 lines
673 B
Verilog
36 lines
673 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (clk);
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input clk;
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int side_effect;
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function int f1;
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input int in;
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f1 = in + 1;
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side_effect += in + 1;
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endfunction
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initial begin
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int got;
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side_effect = 1;
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//
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got = f1(10);
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if (got != 11) $stop;
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if (side_effect != 12) $stop;
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//
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f1(20);
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if (side_effect != 33) $stop;
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//
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// void'f1(30);
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// if (side_effect != 64) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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