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46 lines
1.0 KiB
Verilog
46 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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// bug598
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module t (/*AUTOARG*/
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// Outputs
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val,
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// Inputs
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clk
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);
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input clk;
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output integer val;
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integer dbg_addr = 0;
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function func1;
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input en;
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input [31:0] a;
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func1 = en && (a == 1);
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endfunction
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function func2;
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input en;
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input [31:0] a;
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func2 = en && (a == 2);
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endfunction
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always @(posedge clk) begin
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case( 1'b1 )
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// This line is OK:
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func1(1'b1, dbg_addr) : val = 1;
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// This fails:
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// %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement
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// %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
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func2(1'b1, dbg_addr) : val = 2;
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default : val = 0;
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endcase
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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