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116 lines
2.5 KiB
Verilog
116 lines
2.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [31:0] inp = crc[31:0];
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wire reset = (cyc < 5);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] outp; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.outp (outp[31:0]),
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// Inputs
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.reset (reset),
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.clk (clk),
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.inp (inp[31:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, outp};
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// What checksum will we end up with
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`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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outp,
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// Inputs
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reset, clk, inp
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);
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input reset;
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input clk;
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input [31:0] inp;
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output [31:0] outp;
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function [31:0] no_inline_function;
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input [31:0] var1;
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input [31:0] var2;
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/*verilator no_inline_task*/
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reg [31*2:0] product1 ;
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reg [31*2:0] product2 ;
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integer i;
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reg [31:0] tmp;
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begin
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product2 = {(31*2+1){1'b0}};
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for (i = 0; i < 32; i = i + 1)
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if (var2[i]) begin
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product1 = { {31*2+1-32{1'b0}}, var1} << i;
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product2 = product2 ^ product1;
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end
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no_inline_function = 0;
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for (i= 0; i < 31; i = i + 1 )
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no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
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end
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endfunction
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reg [31:0] outp;
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reg [31:0] inp_d;
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always @( posedge clk ) begin
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if( reset ) begin
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outp <= 0;
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end
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else begin
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inp_d <= inp;
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outp <= no_inline_function(inp, inp_d);
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end
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end
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endmodule
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